Startup, Imec Shrink SRAM Cells – EE Times

EE TimesA team from Unisantis and Imec is using the startup’s so-called Surrounding Gate Transistor with a 50-nm minimum pillar pitch. The design is suited to a 5nm SRAM but is less optimal for logic because it would require three of the transistors to provide … and more …read more Source:: Startup Tech News From […]

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